X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Fadd0.py;h=db04506cfb35335176cf4ef6a66dbc945a083ffb;hb=f09f35af37956dc1e3cc01aadc84ad07a711d2d4;hp=f380d3e5e5c1411759604040e822fdd83777a926;hpb=da918b3777224f5fe562d23eebc3b110261a8c8f;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index f380d3e5..db04506c 100644
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -5,8 +5,8 @@
 from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumBase
-from fpbase import FPState
+from ieee754.fpcommon.fpbase import FPNumBase
+from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData