X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Fpipeline.py;h=7b37a6877d797ee2b0a0d4f03556ec3c151e4981;hb=b2672aebd8aac9aac3a2769b9a0ce509e86b0da6;hp=e244ee60e2f373d917de6eaeaca4a6e7f74d9f32;hpb=b1b03478dedc69a06b76e2da3357884369883063;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index e244ee60..7b37a687 100644
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -5,18 +5,18 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
-from fpcommon.getop import FPADDBaseData
-from fpcommon.denorm import FPSCData
-from fpcommon.pack import FPPackData
-from fpcommon.normtopack import FPNormToPack
-from fpadd.specialcases import FPAddSpecialCasesDeNorm
-from fpadd.addstages import FPAddAlignSingleAdd
-
-from concurrentunit import ReservationStations, num_bits
+from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
+from nmutil.multipipe import CombMuxOutPipe
+from nmutil.multipipe import PriorityCombMuxInPipe
+from nmutil.concurrentunit import ReservationStations, num_bits
+
+from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.pack import FPPackData
+from ieee754.fpcommon.normtopack import FPNormToPack
+from .specialcases import FPAddSpecialCasesDeNorm
+from .addstages import FPAddAlignSingleAdd
+
 
 
 class FPADDBasePipe(ControlBase):