X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Ftest%2Ftest_add.py;h=cd2783c326686809d0ddf7ec5f32104682e76a65;hb=9d42803631201ea445052fb41fe0f1cc5a3a2b14;hp=f09804cd21e4e2bd05916c962f5738d3537570e3;hpb=b2672aebd8aac9aac3a2769b9a0ce509e86b0da6;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/test/test_add.py b/src/ieee754/fpadd/test/test_add.py
index f09804cd..cd2783c3 100644
--- a/src/ieee754/fpadd/test/test_add.py
+++ b/src/ieee754/fpadd/test/test_add.py
@@ -8,10 +8,10 @@ from ieee754.fpadd.nmigen_add_experiment import FPADD
 from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent,
                                 get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
-                                match, get_rs_case, check_rs_case, run_test,
+                                match, get_rs_case, check_rs_case, run_fpunit,
                                 run_edge_cases, run_corner_cases)
 
-def testbench(dut):
+def tbench(dut, maxcount, num_loops):
     yield from check_rs_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
     yield from check_rs_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
     yield from check_rs_case(dut, 0x00000047, 0x80000048, 0x80000001)
@@ -66,14 +66,17 @@ def testbench(dut):
     stimulus_b = [0xff800001, 0xadd79efa, 0xC0000000, 0x1c800000,
                   0xc038ed3a, 0xb328cd45, 
                     0x114f3db, 0x2f642a39, 0xff3807ab]
-    yield from run_test(dut, stimulus_a, stimulus_b, add, get_rs_case)
+    yield from run_fpunit(dut, stimulus_a, stimulus_b, add, get_rs_case)
     count += len(stimulus_a)
     print (count, "vectors passed")
 
     yield from run_corner_cases(dut, count, add, get_rs_case)
-    yield from run_edge_cases(dut, count, add, get_rs_case)
+    yield from run_edge_cases(dut, count, add, get_rs_case, maxcount, num_loops)
 
-if __name__ == '__main__':
+def test1(maxcount=10, num_loops=5):
     dut = FPADD(width=32, id_wid=5, single_cycle=True)
-    run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
+    run_simulation(dut, tbench(dut, maxcount, num_loops),
+                        vcd_name="test_add.vcd")
 
+if __name__ == '__main__':
+    test1(maxcount=1000, num_loops=1000)