X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Ftest%2Ftest_add.py;h=f09804cd21e4e2bd05916c962f5738d3537570e3;hb=b2672aebd8aac9aac3a2769b9a0ce509e86b0da6;hp=989cf482c92ce15dcba4619dbbd7c2f855ad09a9;hpb=17920e72ea4e212030671b0077b16c0719fc5059;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/test/test_add.py b/src/ieee754/fpadd/test/test_add.py
index 989cf482..f09804cd 100644
--- a/src/ieee754/fpadd/test/test_add.py
+++ b/src/ieee754/fpadd/test/test_add.py
@@ -3,9 +3,10 @@ from operator import add
 from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 
-from nmigen_add_experiment import FPADD
+from ieee754.fpadd.nmigen_add_experiment import FPADD
 
-from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
+from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent,
+                                get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
                                 match, get_rs_case, check_rs_case, run_test,
                                 run_edge_cases, run_corner_cases)