X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Ftest%2Ftest_fpadd_pipe.py;h=2b021924fe396145110e9dfcdf2ed26f5306ace8;hb=fe8def53014d725fe6cc716858aa9a640c7db582;hp=df25e55fe7a2f63992ffad68f6cfbe47faa9bd1c;hpb=e71ebd7c7df6fed881f1a5cea15ae1d7b022cd28;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/test/test_fpadd_pipe.py b/src/ieee754/fpadd/test/test_fpadd_pipe.py
index df25e55f..2b021924 100644
--- a/src/ieee754/fpadd/test/test_fpadd_pipe.py
+++ b/src/ieee754/fpadd/test/test_fpadd_pipe.py
@@ -11,7 +11,7 @@ from nmigen import Module, Signal, Cat, Value
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from nmigen_add_experiment import (FPADDMuxInOut,)
+from ieee754.fpadd.nmigen_add_experiment import (FPADDMuxInOut,)
 
 from sfpy import Float32
 
@@ -37,7 +37,7 @@ class InputTest:
     def send(self, mid):
         for i in range(self.tlen):
             op1, op2 = self.di[mid][i]
-            rs = dut.p[mid]
+            rs = self.dut.p[mid]
             yield rs.valid_i.eq(1)
             yield rs.data_i.a.eq(op1)
             yield rs.data_i.b.eq(op2)
@@ -108,8 +108,7 @@ class InputTest:
         print ("recv ended", mid)
 
 
-
-if __name__ == '__main__':
+def test1():
     dut = FPADDMuxInOut(32, 4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_fpadd_pipe.il", "w") as f:
@@ -124,3 +123,5 @@ if __name__ == '__main__':
                         ],
                    vcd_name="test_fpadd_pipe.vcd")
 
+if __name__ == '__main__':
+    test1()