X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpdiv%2Fnmigen_div_experiment.py;h=7887a5273aa2ad98696f6cc48aa028c1f8c3075e;hb=f09f35af37956dc1e3cc01aadc84ad07a711d2d4;hp=a19decd5850b2c54c8205b2aeb89d8a8d8ebfb97;hpb=e71ebd7c7df6fed881f1a5cea15ae1d7b022cd28;p=ieee754fpu.git

diff --git a/src/ieee754/fpdiv/nmigen_div_experiment.py b/src/ieee754/fpdiv/nmigen_div_experiment.py
index a19decd5..7887a527 100644
--- a/src/ieee754/fpdiv/nmigen_div_experiment.py
+++ b/src/ieee754/fpdiv/nmigen_div_experiment.py
@@ -5,7 +5,7 @@
 from nmigen import Module, Signal, Const, Cat
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState
+from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState
 from nmutil.singlepipe import eq
 
 class Div: