X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPeriphery.scala;h=cd658f17dd30625004f39fbfd49113d0e562c483;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hp=f2fe5869201ce660e00bde8bf187cb5aadd5996c;hpb=45c491cd69b3dad347d88fdec3484d51814ee243;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index f2fe586..cd658f1 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -2,27 +2,33 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.util.HeterogeneousBag
 
-trait PeripheryGPIO {
-  this: TopNetwork { val gpioConfig: GPIOConfig } =>
-  val gpio = LazyModule(new TLGPIO(gpioConfig))
-  gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
-  intBus.intnode := gpio.intnode
+case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
+
+trait HasPeripheryGPIO extends HasSystemNetworks {
+  val gpioParams = p(PeripheryGPIOKey)
+  val gpios = gpioParams map {params =>
+    val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
+    gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+    intBus.intnode := gpio.intnode
+    gpio
+  }
 }
 
-trait PeripheryGPIOBundle {
-  this: { val gpioConfig: GPIOConfig } =>
-  val gpio = new GPIOPortIO(gpioConfig)
+trait HasPeripheryGPIOBundle {
+  val gpio: HeterogeneousBag[GPIOPortIO]
 }
 
-trait PeripheryGPIOModule {
-  this: TopNetworkModule {
-    val gpioConfig: GPIOConfig
-    val outer: PeripheryGPIO
-    val io: PeripheryGPIOBundle
-  } =>
-  io.gpio <> outer.gpio.module.io.port
+trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
+  val outer: HasPeripheryGPIO
+  val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
+
+  (gpio zip outer.gpios) foreach { case (io, device) =>
+    io <> device.module.io.port
+  }
 }