X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FJTAG.scala;h=ba40bc663709e102d79d0a638185eedae2d4e8f7;hb=faeb14dc5a6ade086a76a4d02806b3573a974f02;hp=947955f646ee0757c0160db4b1f40095da91b929;hpb=2c47cc4abdf39159a9c91382a13021a8dbf4ca93;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala
index 947955f..ba40bc6 100644
--- a/src/main/scala/devices/gpio/JTAG.scala
+++ b/src/main/scala/devices/gpio/JTAG.scala
@@ -13,28 +13,28 @@ import Chisel._
 import config._
 import jtag.{JTAGIO}
 
-class JTAGPinsIO extends Bundle {
+class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle {
 
   val TCK    = new GPIOPin()
   val TMS    = new GPIOPin()
   val TDI    = new GPIOPin()
   val TDO    = new GPIOPin()
-  val TRSTn  = new GPIOPin()
+  val TRSTn  = if (hasTRSTn) Option(new GPIOPin()) else None
 
 }
 
-class JTAGGPIOPort()(implicit p: Parameters) extends Module {
+class JTAGGPIOPort(hasTRSTn: Boolean = true)(implicit p: Parameters) extends Module {
 
   val io = new Bundle {
     // TODO: make this not hard-coded true.
-    val jtag = new JTAGIO(hasTRSTn = true)
-    val pins = new JTAGPinsIO()
+    val jtag = new JTAGIO(hasTRSTn)
+    val pins = new JTAGPinsIO(hasTRSTn)
   }
 
   io.jtag.TCK  := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
   io.jtag.TMS  := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
   io.jtag.TDI  := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
-  io.jtag.TRSTn.get := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
+  io.jtag.TRSTn.foreach{t => t := GPIOInputPinCtrl(io.pins.TRSTn.get, pue = Bool(true))}
 
   GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
   io.pins.TDO.o.oe := io.jtag.TDO.driven