X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=c9de71b1755cd2557cb5b77419daccbe7b2c9538;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hp=775eb80380b66644ea09f39e8bee55342db7dd83;hpb=64bff444622bf7a61a84ed6cdda8aa6ddd5119cf;p=sifive-blocks.git diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala index 775eb80..c9de71b 100644 --- a/src/main/scala/devices/i2c/I2CPeriphery.scala +++ b/src/main/scala/devices/i2c/I2CPeriphery.scala @@ -2,14 +2,14 @@ package sifive.blocks.devices.i2c import Chisel._ -import config.Field -import diplomacy.LazyModule -import rocketchip.{HasTopLevelNetworks,HasTopLevelNetworksBundle,HasTopLevelNetworksModule} -import uncore.tilelink2.TLFragmenter +import freechips.rocketchip.config.Field +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} +import freechips.rocketchip.chip.{HasSystemNetworks} +import freechips.rocketchip.tilelink.TLFragmenter case object PeripheryI2CKey extends Field[Seq[I2CParams]] -trait HasPeripheryI2C extends HasTopLevelNetworks { +trait HasPeripheryI2C extends HasSystemNetworks { val i2cParams = p(PeripheryI2CKey) val i2c = i2cParams map { params => val i2c = LazyModule(new TLI2C(peripheryBusBytes, params)) @@ -19,15 +19,15 @@ trait HasPeripheryI2C extends HasTopLevelNetworks { } } -trait HasPeripheryI2CBundle extends HasTopLevelNetworksBundle{ - val outer: HasPeripheryI2C - val i2cs = Vec(outer.i2cParams.size, new I2CPort) +trait HasPeripheryI2CBundle { + val i2c: Vec[I2CPort] } -trait HasPeripheryI2CModule extends HasTopLevelNetworksModule { +trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle { val outer: HasPeripheryI2C - val io: HasPeripheryI2CBundle - (io.i2cs zip outer.i2c).foreach { case (io, device) => + val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort)) + + (i2cs zip outer.i2c).foreach { case (io, device) => io <> device.module.io.port } }