X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=c9de71b1755cd2557cb5b77419daccbe7b2c9538;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hp=8eb741873cc6c920069a2a4fb033fc91048d6e31;hpb=9d2a173b15ff2f9c546d95261fd171cf6da51328;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 8eb7418..c9de71b 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -2,33 +2,32 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.{HasSystemNetworks}
+import freechips.rocketchip.tilelink.TLFragmenter
 
-trait PeripheryI2C {
-  this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2cDevices = i2cConfigs.zipWithIndex.map { case (c, i) =>
-    val i2c = LazyModule(new TLI2C(c))
-    i2c.suggestName(s"i2c$i")
-    i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+case object PeripheryI2CKey extends Field[Seq[I2CParams]]
+
+trait HasPeripheryI2C extends HasSystemNetworks {
+  val i2cParams = p(PeripheryI2CKey)
+  val i2c = i2cParams map { params =>
+    val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
+    i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := i2c.intnode
     i2c
   }
 }
 
-trait PeripheryI2CBundle {
-  this: { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2cs = Vec(i2cConfigs.size, new I2CPort)
+trait HasPeripheryI2CBundle {
+  val i2c: Vec[I2CPort]
 }
 
-trait PeripheryI2CModule {
-  this: TopNetworkModule {
-    val i2cConfigs: Seq[I2CConfig]
-    val outer: PeripheryI2C
-    val io: PeripheryI2CBundle
-  } =>
-  (io.i2cs zip outer.i2cDevices).foreach { case (io, device) =>
+trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
+  val outer: HasPeripheryI2C
+  val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
+
+  (i2cs zip outer.i2c).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }