X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPins.scala;h=a4016f3c71a2fdca986a996c124826144c0b8480;hb=81e301f9f75bfdb495d72951f33cada08786d83a;hp=d7017bca46f249010bf648bd2613baa94aa0472c;hpb=a915e84a9ee5fc195051c518f946322037e7cdb5;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index d7017bc..a4016f3 100644
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -2,26 +2,34 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
+import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 
+class I2CSignals[T <: Data](pingen: () => T) extends Bundle {
 
-class I2CPinsIO extends Bundle {
-  val scl = new GPIOPin
-  val sda = new GPIOPin
+  val scl: T = pingen()
+  val sda: T = pingen()
+
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 }
 
-class I2CGPIOPort(syncStages: Int = 0) extends Module {
-  val io = new Bundle{
-    val i2c = new I2CPort().flip()
-    val pins = new I2CPinsIO
-  }
+class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen)
 
-  GPIOOutputPinCtrl(io.pins.scl, io.i2c.scl.out, pue=true.B, ie = true.B)
-  io.pins.scl.o.oe := io.i2c.scl.oe
-  io.i2c.scl.in := ShiftRegisterInit(io.pins.scl.i.ival, syncStages, Bool(true))
+object I2CPinsFromPort {
 
-  GPIOOutputPinCtrl(io.pins.sda, io.i2c.sda.out, pue=true.B, ie = true.B)
-  io.pins.sda.o.oe := io.i2c.sda.oe
-  io.i2c.sda.in := ShiftRegisterInit(io.pins.sda.i.ival, syncStages, Bool(true))
+  def apply[T <: Pin](pins: I2CSignals[T], i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+    withClockAndReset(clock, reset) {
+      pins.scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
+      pins.scl.o.oe := i2c.scl.oe
+      i2c.scl.in := SyncResetSynchronizerShiftReg(pins.scl.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_scl_sync"))
+
+      pins.sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
+      pins.sda.o.oe := i2c.sda.oe
+      i2c.sda.in := SyncResetSynchronizerShiftReg(pins.sda.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_sda_sync"))
+    }
+  }
 }