X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fmockaon%2FMockAON.scala;h=0606822003749b6c2773cd1a25c79bbe29e85ccb;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=914a92c7aef6c1bd4e7ca6c907d66dce0c4cdda8;hpb=7916ef5249c72a3a84c599d123760f4d716de58a;p=sifive-blocks.git

diff --git a/src/main/scala/devices/mockaon/MockAON.scala b/src/main/scala/devices/mockaon/MockAON.scala
index 914a92c..0606822 100644
--- a/src/main/scala/devices/mockaon/MockAON.scala
+++ b/src/main/scala/devices/mockaon/MockAON.scala
@@ -2,16 +2,16 @@
 package sifive.blocks.devices.mockaon
 
 import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
-import rocketchip.PeripheryBusConfig
+import chisel3.experimental.MultiIOModule
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
 
 import sifive.blocks.util.GenericTimer
 
-case class MockAONConfig(
-  address: BigInt = BigInt(0x10000000),
-  nBackupRegs: Int = 16) {
+case class MockAONParams(
+    address: BigInt = BigInt(0x10000000),
+    nBackupRegs: Int = 16) {
   def size: Int = 0x1000
   def regBytes: Int = 4
   def wdogOffset: Int = 0
@@ -20,12 +20,6 @@ case class MockAONConfig(
   def pmuOffset: Int = 0x100
 }
 
-trait HasMockAONParameters {
-  val params: (MockAONConfig, Parameters)
-  val c = params._1
-  implicit val p = params._2
-}
-
 class MockAONPMUIO extends Bundle {
   val vddpaden = Bool(OUTPUT)
   val dwakeup = Bool(INPUT)
@@ -36,10 +30,10 @@ class MockAONMOffRstIO extends Bundle {
   val corerst = Bool(OUTPUT)
 }
 
-trait MockAONBundle extends Bundle with HasMockAONParameters {
+trait HasMockAONBundleContents extends Bundle {
 
   // Output of the Power Management Sequencer
-  val moff = new MockAONMOffRstIO ()
+  val moff = new MockAONMOffRstIO
 
   // This goes out to wrapper
   // to be combined to create aon_rst.
@@ -56,8 +50,10 @@ trait MockAONBundle extends Bundle with HasMockAONParameters {
   val resetCauses = new ResetCauses().asInput
 }
 
-trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
-  val io: MockAONBundle
+trait HasMockAONModuleContents extends MultiIOModule with HasRegMap {
+  val io: HasMockAONBundleContents
+  val params: MockAONParams
+  val c = params
 
   // the expectation here is that Chisel's implicit reset is aonrst,
   // which is asynchronous, so don't use synchronous-reset registers.
@@ -99,7 +95,7 @@ trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
 
 }
 
-class MockAON(c: MockAONConfig)(implicit val p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes, concurrency = 1)(
-  new TLRegBundle((c, p), _)    with MockAONBundle)(
-  new TLRegModule((c, p), _, _) with MockAONModule)
+class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
+  extends TLRegisterRouter(c.address, "aon", Seq("sifive,aon0"), interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
+  new TLRegBundle(c, _)    with HasMockAONBundleContents)(
+  new TLRegModule(c, _, _) with HasMockAONModuleContents)