X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fmockaon%2FMockAONPeriphery.scala;h=8de7ad9ba1d20a85d870241b3d40c7ebe84097d2;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=8b6303e2ffb32f03abe1e8cecfe88aef2548216c;hpb=9ae6413273bcb498af3a9542e0f4dffe084eee83;p=sifive-blocks.git

diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index 8b6303e..8de7ad9 100644
--- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@ -3,10 +3,11 @@ package sifive.blocks.devices.mockaon
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.devices.debug.HasPeripheryDebug
 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
 import freechips.rocketchip.util.ResetCatchAndSync
 
@@ -31,7 +32,7 @@ trait HasPeripheryMockAONBundle {
   }
 }
 
-trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripheryMockAONBundle {
+trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
   val outer: HasPeripheryMockAON
   val aon = IO(new MockAONWrapperBundle)
 
@@ -42,7 +43,12 @@ trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
   outer.aon.module.clock := Bool(false).asClock
   outer.aon.module.reset := Bool(true)
 
-  outer.clint.module.io.rtcTick := outer.aon.module.io.rtc.asUInt.toBool
+  // Synchronize the external toggle into the clint
+  val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
+  val rtc_last = Reg(init = Bool(false), next=rtc_sync)
+  val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
+
+  outer.clint.module.io.rtcTick := rtc_tick
 
   outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
 }