X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWM.scala;h=638100496dabfb564b597a335d05e57c68aef041;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=7bf8d2978950c2c47d426869ba3cb7ace7aeb386;hpb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala
index 7bf8d29..6381004 100644
--- a/src/main/scala/devices/pwm/PWM.scala
+++ b/src/main/scala/devices/pwm/PWM.scala
@@ -2,12 +2,12 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import Chisel.ImplicitConversions._
-import config.Parameters
-import regmapper._
-import uncore.tilelink2._
-import util._
-
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
 import sifive.blocks.util.GenericTimer
 
 // Core PWM Functionality  & Register Interface
@@ -45,11 +45,11 @@ case class PWMParams(
   cmpWidth: Int = 16)
 
 trait HasPWMBundleContents extends Bundle {
-  val params: PWMParams
+  def params: PWMParams
   val gpio = Vec(params.ncmp, Bool()).asOutput
 }
 
-trait HasPWMModuleContents extends Module with HasRegMap {
+trait HasPWMModuleContents extends MultiIOModule with HasRegMap {
   val io: HasPWMBundleContents
   val params: PWMParams
 
@@ -62,6 +62,6 @@ trait HasPWMModuleContents extends Module with HasRegMap {
 }
 
 class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = w)(
+  extends TLRegisterRouter(c.address, "pwm", Seq("sifive,pwm0"), interrupts = c.ncmp, size = c.size, beatBytes = w)(
   new TLRegBundle(c, _)    with HasPWMBundleContents)(
   new TLRegModule(c, _, _) with HasPWMModuleContents)