X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWM.scala;h=c649e7e376eec6cf7e48737a50291bf123ddb69a;hb=45c491cd69b3dad347d88fdec3484d51814ee243;hp=2fd870c6797b239dcf8fb636337a707e0f2acc23;hpb=1443834186bad8981ed29801d3703c05218ce6dc;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala
index 2fd870c..c649e7e 100644
--- a/src/main/scala/devices/pwm/PWM.scala
+++ b/src/main/scala/devices/pwm/PWM.scala
@@ -56,9 +56,9 @@ case class PWMBundleConfig(
 }
 
 trait HasPWMParameters {
-  val params: (PWMConfig, Parameters)
-  val c = params._1
-  implicit val p = params._2
+  implicit val p: Parameters
+  val params: PWMConfig
+  val c = params
 }
 
 trait PWMBundle extends Bundle with HasPWMParameters {
@@ -76,7 +76,7 @@ trait PWMModule extends Module with HasRegMap with HasPWMParameters {
   regmap((GenericTimer.timerRegMap(pwm, 0, c.regBytes)):_*)
 }
 
-class TLPWM(c: PWMConfig)(implicit val p: Parameters)
+class TLPWM(c: PWMConfig)(implicit p: Parameters)
   extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes)(
-  new TLRegBundle((c, p), _)    with PWMBundle)(
-  new TLRegModule((c, p), _, _) with PWMModule)
+  new TLRegBundle(c, _)    with PWMBundle)(
+  new TLRegModule(c, _, _) with PWMModule)