X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=00043ab97abd245c014fa5cc5127e23b7de2f99f;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=7e616da39ffc0fff226923f1b72d04eb22bde383;hpb=25356957fec64ecbae15b7fa85e1d3e536bbce1b;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 7e616da..00043ab 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -2,58 +2,40 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
-
-import sifive.blocks.devices.gpio._
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
+import sifive.blocks.devices.pinctrl.{Pin}
 
-class PWMPortIO(c: PWMParams) extends Bundle {
+class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPinsIO(c: PWMParams) extends Bundle {
-  val pwm = Vec(c.ncmp, new GPIOPin)
-}
-
-class PWMGPIOPort(c: PWMParams) extends Module {
-  val io = new Bundle {
-    val pwm = new PWMPortIO(c).flip()
-    val pins = new PWMPinsIO(c)
-  }
-
-  GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
-}
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-trait HasPeripheryPWM extends HasTopLevelNetworks {
+trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
   val pwmParams = p(PeripheryPWMKey)
   val pwms = pwmParams map { params =>
-    val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
-    pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := pwm.intnode
+    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+    pwm.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := pwm.intnode
     pwm
   }
 }
 
-trait HasPeripheryPWMBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripheryPWM
-  val pwms = HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))
+trait HasPeripheryPWMBundle {
+  val pwm: HeterogeneousBag[PWMPortIO]
+
 }
 
-trait HasPeripheryPWMModule extends HasTopLevelNetworksModule {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
   val outer: HasPeripheryPWM
-  val io: HasPeripheryPWMBundle
+  val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
 
-  (io.pwms zip outer.pwms) foreach { case (io, device) =>
+  (pwm zip outer.pwms) foreach { case (io, device) =>
     io.port := device.module.io.gpio
   }
 }