X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=00043ab97abd245c014fa5cc5127e23b7de2f99f;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=94f65dd760e8c5d75537fc380140492a689526d8;hpb=38f537c438224418356c1ef6979c482841a0da4c;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 94f65dd..00043ab 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.pwm
 import Chisel._
 import freechips.rocketchip.config.Field
 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.devices.pinctrl.{Pin}
 
@@ -13,26 +13,6 @@ class PWMPortIO(val c: PWMParams) extends Bundle {
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
-
-  val pwm: Vec[T] = Vec(c.ncmp, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-}
-
-
-class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends PWMSignals[T](pingen, c) {
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-
-  def fromPort(port: PWMPortIO) {
-    (pwm zip port.port)  foreach {case (pin, port) =>
-      pin.outputPin(port)
-    }
-  }
-}
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
@@ -51,7 +31,7 @@ trait HasPeripheryPWMBundle {
 
 }
 
-trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
   val outer: HasPeripheryPWM
   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))