X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=d3e1c5bc8152580001579422bff8d519fee00dae;hb=81e301f9f75bfdb495d72951f33cada08786d83a;hp=86e9ad2f3f8756aca2db7300190f28131faf0497;hpb=c010a1557aba5e1f9dc004c1ad9ec2cb26eabcfd;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 86e9ad2..d3e1c5b 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -2,57 +2,40 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
-import config._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
+import sifive.blocks.devices.pinctrl.{Pin}
 
-import sifive.blocks.devices.gpio._
-
-class PWMPortIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
+class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPinsIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
-  val pwm = Vec(c.ncmp, new GPIOPin)
-}
-
-class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
-  val io = new Bundle {
-    val pwm = new PWMPortIO(c).flip()
-    val pins = new PWMPinsIO(c)
-  }
-
-  GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
-}
 
-trait PeripheryPWM {
-  this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
+case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-  val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
-    val pwm = LazyModule(new TLPWM(c))
-    pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := pwm.intnode
+trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
+  val pwmParams = p(PeripheryPWMKey)
+  val pwms = pwmParams map { params =>
+    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+    pwm.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := pwm.intnode
     pwm
   }
 }
 
-trait PeripheryPWMBundle {
-  this: {
-    val p: Parameters
-    val pwmConfigs: Seq[PWMConfig]
-  } =>
-  val pwm_bc = pwmConfigs.map(_.bc).reduce(_.union(_))
-  val pwms = Vec(pwmConfigs.size, new PWMPortIO(pwm_bc)(p))
+trait HasPeripheryPWMBundle {
+  val pwm: HeterogeneousBag[PWMPortIO]
+
 }
 
-trait PeripheryPWMModule {
-  this: TopNetworkModule {
-    val outer: PeripheryPWM
-    val io: PeripheryPWMBundle
-  } =>
-  (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
+trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+  val outer: HasPeripheryPWM
+  val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+
+  (pwm zip outer.pwms) foreach { case (io, device) =>
     io.port := device.module.io.gpio
   }
 }