X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=d3e1c5bc8152580001579422bff8d519fee00dae;hb=81e301f9f75bfdb495d72951f33cada08786d83a;hp=d22de54db38ef82091e55e0600ba34e696c858c3;hpb=8bfda688581488468611dbc46c750fd0910a6e5a;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index d22de54..d3e1c5b 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -2,59 +2,40 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
-
-import sifive.blocks.devices.gpio._
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
+import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPinsIO(val c: PWMParams) extends Bundle {
-  val pwm = Vec(c.ncmp, new GPIOPin)
-}
-
-class PWMGPIOPort(val c: PWMParams) extends Module {
-  val io = new Bundle {
-    val pwm = new PWMPortIO(c).flip()
-    val pins = new PWMPinsIO(c)
-  }
-
-  GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
-}
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-trait HasPeripheryPWM extends HasSystemNetworks {
+trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
   val pwmParams = p(PeripheryPWMKey)
   val pwms = pwmParams map { params =>
-    val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
-    pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := pwm.intnode
+    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+    pwm.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := pwm.intnode
     pwm
   }
 }
 
 trait HasPeripheryPWMBundle {
-  val pwms: HeterogeneousBag[PWMPortIO]
+  val pwm: HeterogeneousBag[PWMPortIO]
 
-  def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
-    val pins = Module(new PWMGPIOPort(p.c))
-    pins.io.pwm <> p
-    pins.io.pins
-  }
 }
 
 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
   val outer: HasPeripheryPWM
-  val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+  val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
 
-  (pwms zip outer.pwms) foreach { case (io, device) =>
+  (pwm zip outer.pwms) foreach { case (io, device) =>
     io.port := device.module.io.gpio
   }
 }