X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=b2edb0f64f14d2f9009af8d34cfbc56d6992a953;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=1509ea73c7a38bfae1cb3e3182a8ee4f2aad9636;hpb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 1509ea7..b2edb0f 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -2,58 +2,64 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
-import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
+import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
-trait HasPeripherySPI extends HasTopLevelNetworks {
+trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
   val spiParams = p(PeripherySPIKey)  
   val spis = spiParams map { params =>
-    val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
-    spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := spi.intnode
+    val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
+    spi.rnode := pbus.toVariableWidthSlaves
+    ibus.fromSync := spi.intnode
     spi
   }
 }
 
-trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripherySPI
-  val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
+trait HasPeripherySPIBundle {
+  val spi: HeterogeneousBag[SPIPortIO]
+
 }
 
-trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
   val outer: HasPeripherySPI
-  val io: HasPeripherySPIBundle
-  (io.spis zip outer.spis).foreach { case (io, device) =>
+  val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+
+  (spi zip outer.spis).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
 
-case object PeripherySPIFlashKey extends Field[SPIFlashParams]
+case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait HasPeripherySPIFlash extends HasTopLevelNetworks {
+trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
   val spiFlashParams = p(PeripherySPIFlashKey)  
-  val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams))
-  qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-  qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
-  intBus.intnode := qspi.intnode
+  val qspis = spiFlashParams map { params =>
+    val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+    qspi.rnode := pbus.toVariableWidthSlaves
+    qspi.fnode :=
+      TLFragmenter(1, pbus.blockBytes)(
+      TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
+      pbus.toFixedWidthSlaves))
+    ibus.fromSync := qspi.intnode
+    qspi
+  }
 }
 
-trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripherySPIFlash 
-  val qspi = new SPIPortIO(outer.spiFlashParams)
+trait HasPeripherySPIFlashBundle {
+  val qspi: HeterogeneousBag[SPIPortIO]
+
 }
 
-trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
   val outer: HasPeripherySPIFlash
-  val io: HasPeripherySPIFlashBundle
-  io.qspi <> outer.qspi.module.io.port
+  val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
+
+  (qspi zip outer.qspis) foreach { case (io, device) => 
+    io <> device.module.io.port
+  }
 }