X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=b2edb0f64f14d2f9009af8d34cfbc56d6992a953;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=f2b3b4198fc1e7ce96b02d612581c38f5d5dca2e;hpb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index f2b3b41..b2edb0f 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -3,19 +3,19 @@ package sifive.blocks.devices.spi
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
+import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
 import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
-trait HasPeripherySPI extends HasSystemNetworks {
+trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
   val spiParams = p(PeripherySPIKey)  
   val spis = spiParams map { params =>
-    val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
-    spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := spi.intnode
+    val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
+    spi.rnode := pbus.toVariableWidthSlaves
+    ibus.fromSync := spi.intnode
     spi
   }
 }
@@ -25,7 +25,7 @@ trait HasPeripherySPIBundle {
 
 }
 
-trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
+trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
   val outer: HasPeripherySPI
   val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
 
@@ -36,13 +36,16 @@ trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPI
 
 case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait HasPeripherySPIFlash extends HasSystemNetworks {
+trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
   val spiFlashParams = p(PeripherySPIFlashKey)  
   val qspis = spiFlashParams map { params =>
-    val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
-    qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
-    intBus.intnode := qspi.intnode
+    val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+    qspi.rnode := pbus.toVariableWidthSlaves
+    qspi.fnode :=
+      TLFragmenter(1, pbus.blockBytes)(
+      TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
+      pbus.toFixedWidthSlaves))
+    ibus.fromSync := qspi.intnode
     qspi
   }
 }
@@ -52,7 +55,7 @@ trait HasPeripherySPIFlashBundle {
 
 }
 
-trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
+trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
   val outer: HasPeripherySPIFlash
   val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
 
@@ -60,4 +63,3 @@ trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeriphe
     io <> device.module.io.port
   }
 }
-