X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=f2b3b4198fc1e7ce96b02d612581c38f5d5dca2e;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hp=83e6664b2819c5bdcb4912e87b2c869134fc8002;hpb=dacca7e7b127f5578373c8aa28195ae189d81e51;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 83e6664..f2b3b41 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -2,11 +2,11 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
@@ -21,20 +21,15 @@ trait HasPeripherySPI extends HasSystemNetworks {
 }
 
 trait HasPeripherySPIBundle {
-  val spis: HeterogeneousBag[SPIPortIO]
+  val spi: HeterogeneousBag[SPIPortIO]
 
-  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = spis.map { s =>
-    val pins = Module(new SPIGPIOPort(s.c, syncStages))
-    pins.io.spi <> s
-    pins.io.pins
-  }
 }
 
 trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
   val outer: HasPeripherySPI
-  val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+  val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
 
-  (spis zip outer.spis).foreach { case (io, device) =>
+  (spi zip outer.spis).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
@@ -43,7 +38,7 @@ case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
 trait HasPeripherySPIFlash extends HasSystemNetworks {
   val spiFlashParams = p(PeripherySPIFlashKey)  
-  val qspi = spiFlashParams map { params =>
+  val qspis = spiFlashParams map { params =>
     val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
     qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
@@ -55,21 +50,13 @@ trait HasPeripherySPIFlash extends HasSystemNetworks {
 trait HasPeripherySPIFlashBundle {
   val qspi: HeterogeneousBag[SPIPortIO]
 
-  // It is important for SPIFlash that the syncStages is agreed upon, because
-  // internally it needs to realign the input data to the output SCK.
-  // Therefore, we rely on the syncStages parameter.
-  def SPIFlashtoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = qspi.map { s =>
-    val pins = Module(new SPIGPIOPort(s.c, syncStages))
-    pins.io.spi <> s
-    pins.io.pins
-  }
 }
 
 trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
   val outer: HasPeripherySPIFlash
   val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
 
-  (qspi zip outer.qspi) foreach { case (io, device) => 
+  (qspi zip outer.qspis) foreach { case (io, device) => 
     io <> device.module.io.port
   }
 }