X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPhysical.scala;h=a9ce0760ce30a793c29522d47d99d4a3db4811b6;hb=eea10f51294af8529b278ea88660037d065495b4;hp=cb26bc99046e3dbeb273b376e397b31c611b5567;hpb=a915e84a9ee5fc195051c518f946322037e7cdb5;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index cb26bc9..a9ce076 100644
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.spi
 import Chisel._
 import sifive.blocks.util.ShiftRegisterInit
 
-class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
+class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
   val fn = Bits(width = 1)
   val stb = Bool()
   val cnt = UInt(width = c.countBits)
@@ -16,12 +16,12 @@ object SPIMicroOp {
   def Delay    = UInt(1, 1)
 }
 
-class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
+class SPIPhyControl(c: SPIParamsBase) extends SPIBundle(c) {
   val sck = new SPIClocking(c)
   val fmt = new SPIFormat(c)
 }
 
-class SPIPhysical(c: SPIConfigBase) extends Module {
+class SPIPhysical(c: SPIParamsBase) extends Module {
   val io = new SPIBundle(c) {
     val port = new SPIPortIO(c)
     val ctrl = new SPIPhyControl(c).asInput
@@ -82,7 +82,7 @@ class SPIPhysical(c: SPIConfigBase) extends Module {
   }
 
   val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
-  val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _)
+  val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _).init
   val txen = txen_in :+ txen_in.last
 
   io.port.sck := sck