X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FTLSPI.scala;h=ea28f8936be87b1d9dd9f5e169b088bdff2f78d6;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=bc920ea3c1e7283d80f20d4c9ed2fdb7d54c3daf;hpb=7916ef5249c72a3a84c599d123760f4d716de58a;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index bc920ea..ea28f89 100644
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -2,15 +2,14 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import config._
-import uncore.tilelink2._
-import diplomacy._
-import regmapper._
-import junctions._
-import rocketchip.PeripheryBusConfig
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
 
-trait SPIConfigBase {
+trait SPIParamsBase {
   val rAddress: BigInt
   val rSize: BigInt
   val rxDepth: Int
@@ -30,10 +29,9 @@ trait SPIConfigBase {
   lazy val txDepthBits = log2Floor(txDepth) + 1
   lazy val rxDepthBits = log2Floor(rxDepth) + 1
 
-  lazy val bc = new SPIBundleConfig(csWidth)
 }
 
-case class SPIConfig(
+case class SPIParams(
     rAddress: BigInt,
     rSize: BigInt = 0x1000,
     rxDepth: Int = 8,
@@ -43,30 +41,18 @@ case class SPIConfig(
     delayBits: Int = 8,
     divisorBits: Int = 12,
     sampleDelay: Int = 2)
-  extends SPIConfigBase {
+  extends SPIParamsBase {
 
   require(frameBits >= 4)
   require(sampleDelay >= 0)
 }
 
-case class SPIBundleConfig(csWidth: Int)
-  {
-    def union(that: SPIBundleConfig): SPIBundleConfig =
-      SPIBundleConfig(scala.math.max(csWidth, that.csWidth))
-
-    def toSPIConfig: SPIConfig = new SPIConfig(rAddress = -1,
-      csWidth = csWidth)
-  }
-
-class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
-
-class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)
+class SPITopModule(c: SPIParamsBase, outer: TLSPIBase)
   extends LazyModuleImp(outer) {
 
-  val io = new Bundle {
+  val io = IO(new Bundle {
     val port = new SPIPortIO(c)
-    val tl = bundle
-  }
+  })
 
   val ctrl = Reg(init = SPIControl.init(c))
 
@@ -83,7 +69,8 @@ class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLS
 
   val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0)))
   val ip = fifo.io.ip
-  io.tl.i(0)(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
+  val (io_int, _) = outer.intnode.out(0)
+  io_int(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
 
   protected val regmapBase = Seq(
     SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)),
@@ -118,14 +105,15 @@ class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLS
       RegField.r(1, ip.rxwm)))
 }
 
-abstract class TLSPIBase(c: SPIConfigBase)(implicit val p: Parameters) extends LazyModule {
+abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
   require(isPow2(c.rSize))
-  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = p(PeripheryBusConfig).beatBytes)
-  val intnode = IntSourceNode(1)
+  val device = new SimpleDevice("spi", Seq("sifive,spi0"))
+  val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
+  val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 }
 
-class TLSPI(c: SPIConfig)(implicit p: Parameters) extends TLSPIBase(c)(p) {
-  lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) {
+class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
+  lazy val module = new SPITopModule(c, this) {
     mac.io.link <> fifo.io.link
     rnode.regmap(regmapBase:_*)
   }