X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUART.scala;h=449f897819a57427a8a8e978569df70745bebe2b;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=0dce16d4c60feb4c56d8b533124373d44cc8d7c9;hpb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 0dce16d..449f897 100644
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -2,10 +2,11 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
-import util._
+import chisel3.experimental.MultiIOModule
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
 
 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
 
@@ -13,6 +14,7 @@ case class UARTParams(
   address: BigInt,
   dataBits: Int = 8,
   stopBits: Int = 2,
+  divisorInit: Int = 0,
   divisorBits: Int = 16,
   oversample: Int = 4,
   nSamples: Int = 3,
@@ -23,6 +25,7 @@ trait HasUARTParameters {
   def c: UARTParams
   def uartDataBits = c.dataBits
   def uartStopBits = c.stopBits
+  def uartDivisorInit = c.divisorInit
   def uartDivisorBits = c.divisorBits
 
   def uartOversample = c.oversample
@@ -32,6 +35,7 @@ trait HasUARTParameters {
   def uartNTxEntries = c.nTxEntries
   def uartNRxEntries = c.nRxEntries
 
+  require(uartDivisorInit != 0) // should have been initialized during instantiation
   require(uartDivisorBits > uartOversample)
   require(uartOversampleFactor > uartNSamples)
 }
@@ -66,10 +70,14 @@ class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
   val out = Reg(init = Bits(1, 1))
   io.out := out
 
+  val plusarg_tx = PlusArg("uart_tx", 1, "Enable/disable the TX to speed up simulation").orR
+
   val busy = (counter =/= UInt(0))
   io.in.ready := io.en && !busy
   when (io.in.fire()) {
-    printf("%c", io.in.bits)
+    printf("UART TX (%x): %c\n", io.in.bits, io.in.bits)
+  }
+  when (io.in.fire() && plusarg_tx) {
     shifter := Cat(io.in.bits, Bits(0, 1))
     counter := Mux1H((0 until uartStopBits).map(i =>
       (io.nstop === UInt(i)) -> UInt(n + i + 1)))
@@ -191,7 +199,7 @@ class UARTInterrupts extends Bundle {
   val txwm = Bool()
 }
 
-trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
+trait HasUARTTopModuleContents extends MultiIOModule with HasUARTParameters with HasRegMap {
   val io: HasUARTTopBundleContents
   implicit val p: Parameters
   def params: UARTParams
@@ -203,8 +211,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
   val rxm = Module(new UARTRx(params))
   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 
-  val divinit = 542 // (62.5MHz / 115200)
-  val div = Reg(init = UInt(divinit, uartDivisorBits))
+  val div = Reg(init = UInt(uartDivisorInit, uartDivisorBits))
 
   private val stopCountBits = log2Up(uartStopBits)
   private val txCountBits = log2Floor(uartNTxEntries) + 1
@@ -260,6 +267,6 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
 
 // Magic TL2 Incantation to create a TL2 UART
 class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
+  extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
   new TLRegBundle(c, _)    with HasUARTTopBundleContents)(
   new TLRegModule(c, _, _) with HasUARTTopModuleContents)