X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUART.scala;h=9b3dfaa37110cb6bdd7c93f7baf99fbda52908c8;hb=46aa6b0ac432431e013b25a24331f21457b025a8;hp=0dce16d4c60feb4c56d8b533124373d44cc8d7c9;hpb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 0dce16d..9b3dfaa 100644
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -260,6 +260,6 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
 
 // Magic TL2 Incantation to create a TL2 UART
 class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
+  extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
   new TLRegBundle(c, _)    with HasUARTTopBundleContents)(
   new TLRegModule(c, _, _) with HasUARTTopModuleContents)