X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUART.scala;h=de2cf554a33c1a4d061317b5f182619cee25fe98;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=9b3dfaa37110cb6bdd7c93f7baf99fbda52908c8;hpb=46aa6b0ac432431e013b25a24331f21457b025a8;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 9b3dfaa..de2cf55 100644
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -2,10 +2,10 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
-import util._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
 
 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
 
@@ -13,6 +13,7 @@ case class UARTParams(
   address: BigInt,
   dataBits: Int = 8,
   stopBits: Int = 2,
+  divisorInit: Int = 0,
   divisorBits: Int = 16,
   oversample: Int = 4,
   nSamples: Int = 3,
@@ -23,6 +24,7 @@ trait HasUARTParameters {
   def c: UARTParams
   def uartDataBits = c.dataBits
   def uartStopBits = c.stopBits
+  def uartDivisorInit = c.divisorInit
   def uartDivisorBits = c.divisorBits
 
   def uartOversample = c.oversample
@@ -32,6 +34,7 @@ trait HasUARTParameters {
   def uartNTxEntries = c.nTxEntries
   def uartNRxEntries = c.nRxEntries
 
+  require(uartDivisorInit != 0) // should have been initialized during instantiation
   require(uartDivisorBits > uartOversample)
   require(uartOversampleFactor > uartNSamples)
 }
@@ -66,10 +69,14 @@ class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
   val out = Reg(init = Bits(1, 1))
   io.out := out
 
+  val plusarg_tx = PlusArg("uart_tx", 1, "Enable/disable the TX to speed up simulation").orR
+
   val busy = (counter =/= UInt(0))
   io.in.ready := io.en && !busy
   when (io.in.fire()) {
-    printf("%c", io.in.bits)
+    printf("UART TX (%x): %c\n", io.in.bits, io.in.bits)
+  }
+  when (io.in.fire() && plusarg_tx) {
     shifter := Cat(io.in.bits, Bits(0, 1))
     counter := Mux1H((0 until uartStopBits).map(i =>
       (io.nstop === UInt(i)) -> UInt(n + i + 1)))
@@ -203,8 +210,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
   val rxm = Module(new UARTRx(params))
   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 
-  val divinit = 542 // (62.5MHz / 115200)
-  val div = Reg(init = UInt(divinit, uartDivisorBits))
+  val div = Reg(init = UInt(uartDivisorInit, uartDivisorBits))
 
   private val stopCountBits = log2Up(uartStopBits)
   private val txCountBits = log2Floor(uartNTxEntries) + 1