X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=95d0c3b4bdb7d7d65345f3990c1e65d9893dd723;hb=38f537c438224418356c1ef6979c482841a0da4c;hp=105592d2042e7a6f19d265d37c45f3e5ff771c46;hpb=06f0d2074237f3fa23275446f1ee74614e61f96e;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 105592d..95d0c3b 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,20 +4,18 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
-import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
 
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
-trait HasPeripheryUART extends HasSystemNetworks {
-  val uartParams = p(PeripheryUARTKey)  
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+  private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
+  val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
   val uarts = uartParams map { params =>
-    val uart = LazyModule(new TLUART(peripheryBusBytes, params))
-    uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := uart.intnode
+    val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+    uart.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := uart.intnode
     uart
   }
 }
@@ -39,20 +37,3 @@ trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUA
     io <> device.module.io.port
   }
 }
-
-class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
-  val rxd = pingen()
-  val txd = pingen()
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
-
-  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
-    withClockAndReset(clock, reset) {
-      txd.outputPin(uart.txd)
-      val rxd_t = rxd.inputPin()
-      uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
-    }
-  }
-}
-