X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIG.scala;h=afaff337e3d67a340ae1b245e5f948ebd12f65a2;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=0ea057f7c179596b7bee31034b56913a112ba9c9;hpb=b882d6da934b8a6f0f1780c0cedfaf54ba7701c8;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 0ea057f..afaff33 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -3,11 +3,11 @@ package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
 import chisel3.experimental.{Analog,attach}
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
 
 trait HasXilinxVC707MIGParameters {
@@ -28,16 +28,23 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
       regionType    = RegionType.UNCACHED,
       executable    = true,
       supportsWrite = TransferSizes(1, 256*8),
-      supportsRead  = TransferSizes(1, 256*8),
-      interleavedId = Some(0))),
+      supportsRead  = TransferSizes(1, 256*8))),
     beatBytes = 8)))
 
-  val xing = LazyModule(new TLAsyncCrossing)
-  val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
+  val xing    = LazyModule(new TLAsyncCrossing)
+  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
+  val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
+  val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
+  val yank    = LazyModule(new AXI4UserYanker)
+  val buffer  = LazyModule(new AXI4Buffer)
 
   xing.node := node
   val monitor = (toaxi4.node := xing.node)
-  axi4 := toaxi4.node
+  axi4 := buffer.node
+  buffer.node := yank.node
+  yank.node := deint.node
+  deint.node := indexer.node
+  indexer.node := toaxi4.node
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
@@ -70,9 +77,8 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     io.port.ddr3_odt          := blackbox.io.ddr3_odt
 
     //inputs
-    //differential system clock
-    blackbox.io.sys_clk_n     := io.port.sys_clk_n
-    blackbox.io.sys_clk_p     := io.port.sys_clk_p
+    //NO_BUFFER clock
+    blackbox.io.sys_clk_i     := io.port.sys_clk_i
 
     //user interface signals
     val axi_async = axi4.bundleIn(0)
@@ -80,9 +86,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     xing.module.io.in_reset := reset
     xing.module.io.out_clock := blackbox.io.ui_clk
     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
-    toaxi4.module.clock := blackbox.io.ui_clk
-    toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
-    monitor.foreach { lm =>
+    (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
       lm.module.clock := blackbox.io.ui_clk
       lm.module.reset := blackbox.io.ui_clk_sync_rst
     }