X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIG.scala;h=afaff337e3d67a340ae1b245e5f948ebd12f65a2;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=f7aa339bab5e850678f217412630e38139ca20a5;hpb=c68e44ec554e47ca07e8f3e42246436779a9764f;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index f7aa339..afaff33 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -2,47 +2,49 @@
 package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
-import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGUnidirectionalIOClocksReset, VC707MIGUnidirectionalIODDR, vc707mig}
+import chisel3.experimental.{Analog,attach}
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
 
 trait HasXilinxVC707MIGParameters {
 }
 
-class XilinxVC707MIGPads extends Bundle with VC707MIGUnidirectionalIODDR {
-  val _inout_ddr3_dq = Bits(OUTPUT,64)
-  val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
-  val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
+class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
 
-class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
-                                      with VC707MIGUnidirectionalIOClocksReset {
-  val _inout_ddr3_dq = Bits(OUTPUT,64)
-  val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
-  val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
+class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
+                                      with VC707MIGIOClocksReset
 
 class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
+  val device = new MemoryDevice
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+      resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,
       supportsWrite = TransferSizes(1, 256*8),
-      supportsRead  = TransferSizes(1, 256*8),
-      interleavedId = Some(0))),
+      supportsRead  = TransferSizes(1, 256*8))),
     beatBytes = 8)))
 
-  val xing = LazyModule(new TLAsyncCrossing)
-  val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
+  val xing    = LazyModule(new TLAsyncCrossing)
+  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
+  val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
+  val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
+  val yank    = LazyModule(new AXI4UserYanker)
+  val buffer  = LazyModule(new AXI4Buffer)
 
   xing.node := node
   val monitor = (toaxi4.node := xing.node)
-  axi4 := toaxi4.node
+  axi4 := buffer.node
+  buffer.node := yank.node
+  yank.node := deint.node
+  deint.node := indexer.node
+  indexer.node := toaxi4.node
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
@@ -56,9 +58,9 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     //pins to top level
 
     //inouts
-    io.port._inout_ddr3_dq    := blackbox.io.ddr3_dq
-    io.port._inout_ddr3_dqs_n := blackbox.io.ddr3_dqs_n
-    io.port._inout_ddr3_dqs_p := blackbox.io.ddr3_dqs_p
+    attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
+    attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
+    attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
 
     //outputs
     io.port.ddr3_addr         := blackbox.io.ddr3_addr
@@ -75,9 +77,8 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     io.port.ddr3_odt          := blackbox.io.ddr3_odt
 
     //inputs
-    //differential system clock
-    blackbox.io.sys_clk_n     := io.port.sys_clk_n
-    blackbox.io.sys_clk_p     := io.port.sys_clk_p
+    //NO_BUFFER clock
+    blackbox.io.sys_clk_i     := io.port.sys_clk_i
 
     //user interface signals
     val axi_async = axi4.bundleIn(0)
@@ -85,9 +86,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     xing.module.io.in_reset := reset
     xing.module.io.out_clock := blackbox.io.ui_clk
     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
-    toaxi4.module.clock := blackbox.io.ui_clk
-    toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
-    monitor.foreach { lm =>
+    (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
       lm.module.clock := blackbox.io.ui_clk
       lm.module.reset := blackbox.io.ui_clk_sync_rst
     }