X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIG.scala;h=c248f6c5553b05f317aee6bbd285bc81c7719e9f;hb=a24fa9b444c3e33e356e83dba07572b26098f17e;hp=0ea057f7c179596b7bee31034b56913a112ba9c9;hpb=6eddf517a38156a22b9b831ba92626673a11d603;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 0ea057f..c248f6c 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -28,16 +28,21 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
       regionType    = RegionType.UNCACHED,
       executable    = true,
       supportsWrite = TransferSizes(1, 256*8),
-      supportsRead  = TransferSizes(1, 256*8),
-      interleavedId = Some(0))),
+      supportsRead  = TransferSizes(1, 256*8))),
     beatBytes = 8)))
 
-  val xing = LazyModule(new TLAsyncCrossing)
-  val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
+  val xing    = LazyModule(new TLAsyncCrossing)
+  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8))
+  val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
+  val deint   = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
+  val yank    = LazyModule(new AXI4UserYanker)
 
   xing.node := node
   val monitor = (toaxi4.node := xing.node)
-  axi4 := toaxi4.node
+  axi4 := yank.node
+  yank.node := deint.node
+  deint.node := indexer.node
+  indexer.node := toaxi4.node
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
@@ -80,9 +85,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     xing.module.io.in_reset := reset
     xing.module.io.out_clock := blackbox.io.ui_clk
     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
-    toaxi4.module.clock := blackbox.io.ui_clk
-    toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
-    monitor.foreach { lm =>
+    (Seq(toaxi4, indexer, deint, yank) ++ monitor) foreach { lm =>
       lm.module.clock := blackbox.io.ui_clk
       lm.module.reset := blackbox.io.ui_clk_sync_rst
     }