X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIGPeriphery.scala;h=5a5fb4f211453055db8768b25e21e6d710c10680;hb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;hp=4586949c0eada15181f58e5c4186f7118fa87841;hpb=03be9aba67b185b5454e9013901e6f873f62ac9d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index 4586949..5a5fb4f 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -3,24 +3,28 @@ package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
 import diplomacy._
-import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
+import rocketchip.{
+  HasTopLevelNetworks,
+  HasTopLevelNetworksModule,
+  HasTopLevelNetworksBundle
+}
 import coreplex.BankedL2Config
 
-trait PeripheryXilinxVC707MIG extends TopNetwork {
-  val module: PeripheryXilinxVC707MIGModule
+trait HasPeripheryXilinxVC707MIG extends HasTopLevelNetworks {
+  val module: HasPeripheryXilinxVC707MIGModule
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
   require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
   xilinxvc707mig.node := mem(0).node
 }
 
-trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
+trait HasPeripheryXilinxVC707MIGBundle extends HasTopLevelNetworksBundle {
   val xilinxvc707mig = new XilinxVC707MIGIO
 }
 
-trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
-  val outer: PeripheryXilinxVC707MIG
-  val io: PeripheryXilinxVC707MIGBundle
+trait HasPeripheryXilinxVC707MIGModule extends HasTopLevelNetworksModule {
+  val outer: HasPeripheryXilinxVC707MIG
+  val io: HasPeripheryXilinxVC707MIGBundle
 
   io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
 }