X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707pciex1%2FXilinxVC707PCIeX1.scala;h=cf8eae744e9408fa46fee00ce7cbb5a37fc5384d;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=f657459637f903ed4c86fb0addafba70b0563815;hpb=64bff444622bf7a61a84ed6cdda8aa6ddd5119cf;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index f657459..cf8eae7 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -2,11 +2,11 @@
 package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.coreplex.CacheBlockBytes
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
 import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
 import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
 
@@ -20,15 +20,38 @@ class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
 }
 
 class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
-  val slave = TLInputNode()
-  val control = TLInputNode()
-  val master = TLOutputNode()
+  val slave = TLAsyncInputNode()
+  val control = TLAsyncInputNode()
+  val master = TLAsyncOutputNode()
   val intnode = IntOutputNode()
 
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
-  axi_to_pcie_x1.slave   := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
-  axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
-  master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
+
+  axi_to_pcie_x1.slave :=
+    AXI4Buffer()(
+    AXI4UserYanker()(
+    AXI4Deinterleaver(p(CacheBlockBytes))(
+    AXI4IdIndexer(idBits=4)(
+    TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
+    TLAsyncCrossingSink()(
+    slave))))))
+
+  axi_to_pcie_x1.control :=
+    AXI4Buffer()(
+    AXI4UserYanker(capMaxFlight = Some(2))(
+    TLToAXI4(beatBytes=4)(
+    TLFragmenter(4, p(CacheBlockBytes))(
+    TLAsyncCrossingSink()(
+    control)))))
+
+  master :=
+    TLAsyncCrossingSource()(
+    TLWidthWidget(8)(
+    AXI4ToTL()(
+    AXI4UserYanker(capMaxFlight=Some(8))(
+    AXI4Fragmenter()(
+    axi_to_pcie_x1.master)))))
+
   intnode := axi_to_pcie_x1.intnode
 
   lazy val module = new LazyModuleImp(this) {