X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Futil%2FRegMapFIFO.scala;h=3e4548242d1b63a0ebde1016d00d68c554a67925;hb=ca7555bd4d868c39cd2d92395c985e57dd3a197a;hp=aaeba59bff55ff651459f42b02c58ba59ce6c140;hpb=b8ecb7853b5f89a812eedfaf5bcea628093c5b69;p=sifive-blocks.git

diff --git a/src/main/scala/util/RegMapFIFO.scala b/src/main/scala/util/RegMapFIFO.scala
index aaeba59..3e45482 100644
--- a/src/main/scala/util/RegMapFIFO.scala
+++ b/src/main/scala/util/RegMapFIFO.scala
@@ -8,18 +8,24 @@ import regmapper._
 object NonBlockingEnqueue {
   def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
     val enqWidth = enq.bits.getWidth
+    val quash = Wire(Bool())
     require(enqWidth > 0)
     require(regWidth > enqWidth)
     Seq(
       RegField(enqWidth,
         RegReadFn(UInt(0)),
         RegWriteFn((valid, data) => {
-          enq.valid := valid
+          enq.valid := valid && !quash
           enq.bits := data
           Bool(true)
         })),
       RegField(regWidth - enqWidth - 1),
-      RegField.r(1, !enq.ready))
+      RegField(1,
+        !enq.ready,
+        RegWriteFn((valid, data) =>  {
+          quash := valid && data(0)
+          Bool(true)
+        })))
   }
 }