X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fnmutil%2Flatch.py;h=6cf5ab7ec93e5de0752cdfd2cf00f56c4edf7d8c;hb=9caed89157be10585ebe5f7734cb479fbacb4240;hp=d845a954331be955681adac188d7e4f05c9ba4b5;hpb=810f03298aa47dae5e427cc794f912bd15305681;p=ieee754fpu.git

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index d845a954..6cf5ab7e 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -21,6 +21,15 @@ always @ (posedge c)
 endmodule
 """
 
+def latchregister(m, incoming, outgoing, settrue):
+    reg = Signal.like(incoming) # make register same as input. reset is OK.
+    with m.If(settrue):
+        m.d.sync += reg.eq(incoming)      # latch input into register
+        m.d.comb += outgoing.eq(incoming) # return input (combinatorial)
+    with m.Else():
+        m.d.comb += outgoing.eq(reg) # return input (combinatorial)
+
+
 class SRLatch(Elaboratable):
     def __init__(self, sync=True):
         self.sync = sync