X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fperipherals%2Fflexbus%2FFlexBus_Types.bsv;h=a21ccf5e6aef5c49179284700dabb07776cacbf4;hb=a25c6287911439a284f0d7afcb875fa0e82e9439;hp=5a7055f859fef5118d6ff0ef2db3303885b92fa8;hpb=8b0ce8a367a9d8aaec8a0b7804185544b18cbcb0;p=shakti-peripherals.git

diff --git a/src/peripherals/flexbus/FlexBus_Types.bsv b/src/peripherals/flexbus/FlexBus_Types.bsv
index 5a7055f..a21ccf5 100644
--- a/src/peripherals/flexbus/FlexBus_Types.bsv
+++ b/src/peripherals/flexbus/FlexBus_Types.bsv
@@ -41,7 +41,7 @@ import GetPut   :: *;
 import SpecialFIFOs:: *;
 import Connectable :: *;
 import ConfigReg :: *;
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
 
 // ----------------
 // BSV additional libs
@@ -49,7 +49,7 @@ import ConfigReg :: *;
 import Semi_FIFOF :: *;
 import AXI4_Types   :: *;
 
-import Memory_AXI4 :: *;
+//import Memory_AXI4 :: *;
 
 // ****************************************************************
 // ****************************************************************
@@ -67,20 +67,19 @@ interface FlexBus_Master_IFC;
    // FlexBus External Signals
   
    // AD inout bus separate for now in BSV
-   (* result="AD"       *) interface Get#(Bit#(32))  m_AD;         // out
-   interface Put#(Bit#(32) m_din;                                  // in
+   interface Get#(Bit#(32))  m_AD;         // out
+   interface Put#(Bit#(32)) m_din;         // in
 
-   (* result="R_Wn"     *) interface Get#(Bit#(1))   m_R_Wn;       // out
-   (* result="R_Wn"     *) interface Get#(Bit#(1))   m_R_Wn;       // out
-   (* result="TSIZ"     *) interface Get#(Bit #(2)   m_TSIZ;       // out
+   interface Get#(Bit#(1))   m_R_Wn;       // out
+   interface Get#(Bit#(2))   m_TSIZ;       // out
 
-   (* result="FBCSn"    *) interface Get#(Bit#(6))   m_FBCSn;      // out
-   (* result="BEn_BWEn" *) interface Get#(Bit#(4))   m_BE_BWEn;    // out
-   (* result="TBSTn"    *) interface Get#(Bit#(1))   m_TBSTn;      // out
-   (* result="OEn"      *) interface Get#(Bit#(1))   m_OEn;        // out
+   interface Get#(Bit#(6))   m_FBCSn;      // out
+   interface Get#(Bit#(4))   m_BE_BWEn;    // out
+   interface Get#(Bit#(1))   m_TBSTn;      // out
+   interface Get#(Bit#(1))   m_OEn;        // out
 
-   (* result="ALE"      *) interface Get#(Bit#(1))   m_ALE;        // out
-   interface Put#(Bit#(1) tAn;                                     // in
+   interface Get#(Bit#(1))   m_ALE;        // out
+   interface Put#(Bit#(1))   tAn;          // in
 
 endinterface: FlexBus_Master_IFC
 
@@ -114,13 +113,12 @@ endinterface: FlexBus_Register_IFC
 // These are the signal-level interfaces for an AXI4-Lite slave.
 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
 // we get exactly the signals specified in the ARM spec.
-(* always_ready, always_enabled    *)
 interface FlexBus_Slave_IFC ;
   
+/*
    (* result="AD"       *) interface Put#(Bit#(32))  m_AD;         // out
    interface Get#(Bit#(32) m_din;                                  // in
 
-   (* result="R_Wn"     *) interface Put#(Bit#(1))   m_R_Wn;       // out
    (* result="R_Wn"     *) interface Put#(Bit#(1))   m_R_Wn;       // out
    (* result="TSIZ"     *) interface Put#(Bit #(2)   m_TSIZ;       // out
 
@@ -131,6 +129,33 @@ interface FlexBus_Slave_IFC ;
 
    (* result="ALE"      *) interface Put#(Bit#(1))   m_ALE;        // out
    interface Get#(Bit#(1) tAn;                                     // in
+*/
+
+   (* always_ready, always_enabled    *)
+   method Action m_AD     ( (* port="AD"      *) Bit #(32) i_AD);      // in
+
+
+   (* always_ready, always_enabled    *) 
+   method Action m_ALE    ( (* port="ALE"     *) Bit #(1)  i_ALE);     // in
+
+   (* always_ready, always_enabled    *) 
+   method Action m_R_Wn   ( (* port="R_Wn"    *) Bit #(1)  i_R_Wn);    // in
+   (* always_ready, always_enabled    *) 
+   method Action m_TSIZ   ( (* port="TSIZ"    *) Bit #(2)  i_TSIZ);    // in
+
+   (* always_ready, always_enabled    *) 
+   method Action m_FBCSn  ( (* port="FBCSn"   *) Bit #(6)  i_FBCSn);   // in
+   (* always_ready, always_enabled    *) 
+   method Action m_BE_BWEn( (* port="BE_BWEn" *) Bit #(4)  i_BE_BWEn); // in
+   (* always_ready, always_enabled    *) 
+   method Action m_TBSTn  ( (* port="TBSTn"   *) Bit #(1)  i_TBSTn);   // in
+   (* always_ready, always_enabled    *) 
+   method Action m_OEn    ( (* port="OEn"     *) Bit #(1)  i_OEn);     // in
+
+   (* always_ready, result="din"   *)  
+   method Bit #(32) m_din;                                             // out
+   (* always_ready, result="TAn"   *)  
+   method Bit #(1) m_TAn;                                              // out
 
 endinterface: FlexBus_Slave_IFC
 
@@ -138,6 +163,7 @@ endinterface: FlexBus_Slave_IFC
 // ================================================================
 // Connecting signal-level interfaces
 
+`ifdef DISABLED_FOR_NOW // TODO. convert to get/put including slave ifc
 instance Connectable #(FlexBus_Master_IFC ,
 		       FlexBus_Slave_IFC  );
 
@@ -173,6 +199,7 @@ instance Connectable #(FlexBus_Master_IFC ,
 
    endmodule
 endinstance
+`endif
 
 // ****************************************************************
 // ****************************************************************
@@ -1046,7 +1073,7 @@ module mkAXI4_Slave_to_FlexBus_Master_Xactor
 interface flexbus_side = interface FlexBus_Master_IFC;
 	    //interface io_AD_master = tri_AD_out.io;
         
-    interface c_TAn = interface Put
+    interface tAn = interface Put
         method Action put(Bit#(1) in) if(c_TAn[0] matches tagged Invalid);
             c_TAn[0] <= tagged Valid in;
         endmethod
@@ -1258,5 +1285,22 @@ interface op_side = interface FlexBus_Register_Output_IFC;
 
 endmodule: mkFlexBus_Registers
 
+`ifdef TESTING
+module mkVerfn_Top (Empty);
+
+/*
+    FlexBus_Slave_to_AXI4_Master_Fabric_IFC#(32,32,4)
+                    verfn_ifc <- mkFlexBus_Slave_to_AXI4_Master_Fabric;
+    AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(32, 32, 4)
+              flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
+
+    mkConnection(flexbus_xactor_ifc.flexbus_side,verfn_ifc.flexbus_side);
+*/
+
+   AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
+          flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
+
+endmodule 
+`endif
 
 endpackage