X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fperipherals%2Fsdram%2Fsdr_top.bsv;h=20e69646baa1a285b8f2de26f3ee648db1f03e13;hb=999a00cb651c843fe869eb954f28b14e7329c7f2;hp=ec1d82167c6112fb7b77f9e8dd93d17cfcbb5e85;hpb=b0f638c4cf2d16dbf62249a253575259261eb3fb;p=shakti-peripherals.git diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index ec1d821..20e6964 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -31,12 +31,12 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND `define SDR_INIT_DONE 8'h58 `define SDR_WIDTH 8'h60 `define SDR_COLBITS 8'h68 -`define SDR_SDIO_CTRL 8'h70 `define SDR_CLK_DELAY 8'h78 `define verbose package sdr_top; +import GetPut:: *; import Semi_FIFOF :: *; import AXI4_Types :: *; import AXI4_Fabric :: *; @@ -49,20 +49,20 @@ import FIFOF::*; import Clocks::*; interface Ifc_sdram_out; - (*always_enabled,always_ready*) - method Action ipad_sdr_din(Bit#(64) pad_sdr_din); - method Bit#(9) sdram_sdio_ctrl(); - method Bit#(64) osdr_dout(); - method Bit#(8) osdr_den_n(); - method Bool osdr_cke(); - method Bool osdr_cs_n(); - method Bool osdr_ras_n (); - method Bool osdr_cas_n (); - method Bool osdr_we_n (); - method Bit#(8) osdr_dqm (); - method Bit#(2) osdr_ba (); - method Bit#(13) osdr_addr (); - interface Clock sdram_clk; + (*always_enabled, always_ready*) + interface Put#(Bit#(64)) ipad_sdr_din; + interface Get#(Bit#(64)) osdr_dout; + interface Get#(Bit#(64)) osdr_den_n; + interface Get#(Bit#(1)) osdr_cke; + interface Get#(Bit#(1)) osdr_cs_n; + interface Get#(Bit#(1)) osdr_ras_n; + interface Get#(Bit#(1)) osdr_cas_n; + interface Get#(Bit#(1)) osdr_we_n; + interface Get#(Bit#(8)) osdr_dqm; + interface Get#(Bit#(2)) osdr_ba; + interface Get#(Bit#(13)) osdr_addr; + interface Get#(Bit#(1)) osdr_clock; + endinterface interface Ifc_sdr_slave; @@ -265,7 +265,6 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); Reg#(Bit#(4)) rg_cfg_sdr_twr_d <- mkConfigReg(4'h1,clocked_by clk0, reset_by rst0); Reg#(Bit#(2)) rg_cfg_sdr_width <- mkConfigReg(2'b0,clocked_by clk0, reset_by rst0); Reg#(Bit#(2)) rg_cfg_colbits <- mkConfigReg(2'b01,clocked_by clk0, reset_by rst0); - Reg#(Bit#(9)) rg_cfg_sdio_ctrl <- mkConfigReg(9'b000100011,clocked_by clk0, reset_by rst0); Reg#(Bit#(8)) rg_cfg_sdr_clk_delay <- mkConfigReg(8'b00001000,clocked_by clk0, reset_by rst0); Reg#(Bit#(`SDR_RFSH_TIMER_W )) rg_cfg_sdr_rfsh <- mkConfigReg(12'h100,clocked_by clk0, reset_by rst0); @@ -372,7 +371,6 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); `SDR_COLBITS : rg_cfg_colbits <= data [1:0]; - `SDR_SDIO_CTRL : rg_cfg_sdio_ctrl <= data [8:0]; `SDR_CLK_DELAY : rg_cfg_sdr_clk_delay <= data [7:0]; @@ -413,7 +411,6 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); `SDR_COLBITS : return extend(rg_cfg_colbits); - `SDR_SDIO_CTRL : return extend(rg_cfg_sdio_ctrl); `SDR_CLK_DELAY : return extend(rg_cfg_sdr_clk_delay); @@ -759,54 +756,83 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); interface Ifc_sdram_out ifc_sdram_out; - method Action ipad_sdr_din(Bit#(64) pad_sdr_din); - sdr_cntrl.ipad_sdr_din(pad_sdr_din); - endmethod - method Bit#(9) sdram_sdio_ctrl(); - return rg_cfg_sdio_ctrl; - endmethod - method Bit#(64) osdr_dout(); + interface ipad_sdr_din = interface Put + method Action put(Bit#(64) in); + sdr_cntrl.ipad_sdr_din <= in; + endmethod + endinterface; + + interface osdr_dout = interface Get + method ActionValue#(Bit#(64)) get; return sdr_cntrl.osdr_dout(); - endmethod - method Bit#(8) osdr_den_n(); - return sdr_cntrl.osdr_den_n(); - endmethod - method Bool osdr_cke(); - return sdr_cntrl.osdr_cke(); - endmethod - - method Bool osdr_cs_n(); - return sdr_cntrl.osdr_cs_n(); - endmethod - - method Bool osdr_ras_n (); - return sdr_cntrl.osdr_ras_n; - endmethod - - method Bool osdr_cas_n (); - return sdr_cntrl.osdr_cas_n; - endmethod - - method Bool osdr_we_n (); - return sdr_cntrl.osdr_we_n; - endmethod - - method Bit#(8) osdr_dqm (); + endmethod + endinterface; + + interface osdr_den_n = interface Get + method ActionValue#(Bit#(64)) get; + Bit#(64) temp; + for (int i=0; i<8; i=i+1) begin + temp[i*8] = sdr_cntrl.osdr_den_n[i]; + end + return temp; + endmethod + endinterface; + + interface osdr_cke = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_cke()); + endmethod + endinterface; + + interface osdr_cs_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_cs_n()); + endmethod + endinterface; + + interface osdr_ras_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_ras_n); + endmethod + endinterface; + + interface osdr_cas_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_cas_n); + endmethod + endinterface; + + interface osdr_we_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_we_n); + endmethod + endinterface; + + interface osdr_dqm = interface Get + method ActionValue#(Bit#(8)) get; return sdr_cntrl.osdr_dqm; - endmethod + endmethod + endinterface; - method Bit#(2) osdr_ba (); + interface osdr_ba = interface Get + method ActionValue#(Bit#(2)) get; return sdr_cntrl.osdr_ba; - endmethod + endmethod + endinterface; - method Bit#(13) osdr_addr (); + interface osdr_addr = interface Get + method ActionValue#(Bit#(13)) get; return sdr_cntrl.osdr_addr; - endmethod - - interface sdram_clk = clk0; + endmethod + endinterface; + + interface osdr_clock = interface Get + method ActionValue#(Bit#(1)) get; + return ?; + endmethod + endinterface; endinterface - interface axi4_slave_sdram = s_xactor_sdram.axi_side; interface axi4_slave_cntrl_reg = s_xactor_cntrl_reg.axi_side;