X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fperipherals%2Fuart%2Fquart.bsv;h=f8aee3dde5d3860e57ad9f0b5a3e166b9f76b90a;hb=a53da17efe5132fbca2641edae167f1348497339;hp=392dcddff25d23d171868e3473e9de663a354868;hpb=6d4e16aebe4a95443fa12972695d86c16096ed6b;p=shakti-peripherals.git

diff --git a/src/peripherals/uart/quart.bsv b/src/peripherals/uart/quart.bsv
index 392dcdd..f8aee3d 100644
--- a/src/peripherals/uart/quart.bsv
+++ b/src/peripherals/uart/quart.bsv
@@ -56,21 +56,17 @@ package quart;
                                         (QUART_AXI4_Lite_Ifc);
 
     Uart16550_AXI4_Lite_Ifc uart <- mkUart16550(core_clock, core_reset);
-    //uart.pin_dsr_sync <= in; 
-    //uart.pin_ri_sync  <= in; 
-    //uart.pin_dcd_sync <= in; 
+
+    // ok set up CDC and dsr to 1, and Ring to 0. and otherwise ignore them
 	rule rl_put;
-    Bit#(1) v1 = 1;
-    Bit#(1) v0 = 1;
-    uart.coe_rs232.dsr_in.put(1);
-    
-    uart.coe_rs232.dcd_in.put(1);
-    uart.coe_rs232.ri_in.put(0);
+        uart.coe_rs232.dsr_in.put(1);
+        uart.coe_rs232.dcd_in.put(1);
+        uart.coe_rs232.ri_in.put(0);
 	endrule
     
-
+    // deliberately drop (ignore) this value
 	rule rl_get;
-    let temp2 <- uart.coe_rs232.dtr_out.get;
+        let temp2 <- uart.coe_rs232.dtr_out.get;
 	endrule
 
     interface out = interface QUART_out