X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fscoreboard%2Fdependence_cell.py;h=d386852e2cb108f1df6d2408bdd2f27b0d0ceb35;hb=42ff5cc0d2fa4aaf0f2cef99735cb9e56e3479c8;hp=c082233abfc2502b949f65476844fa18dfd12f16;hpb=758d6e0abe032cf05a09eafeeedae740b2102196;p=soc.git diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index c082233a..d386852e 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -4,6 +4,49 @@ from nmigen import Module, Signal, Elaboratable, Array, Cat from nmutil.latch import SRLatch +class DepCell(Elaboratable): + """ implements 11.4.7 mitch alsup dependence cell, p27 + adjusted to be clock-sync'd on rising edge only. + mitch design (as does 6600) requires alternating rising/falling clock + """ + def __init__(self): + # inputs + self.reg_i = Signal(reset_less=True) # reg bit in (top) + self.issue_i = Signal(reset_less=True) # Issue in (top) + self.go_i = Signal(reset_less=True) # Go read/write in (left) + + # for Register File Select Lines (vertical) + self.rsel_o = Signal(reset_less=True) # reg sel (bottom) + # for Function Unit "forward progress" (horizontal) + self.fwd_o = Signal(reset_less=True) # FU forard progress (right) + + def elaborate(self, platform): + m = Module() + m.submodules.l = l = SRLatch(sync=False) # async latch + + # reset on go HI, set on dest and issue + m.d.comb += dest_l.s.eq(self.issue_i & self.reg_i) + m.d.comb += dest_l.r.eq(self.go_i) + + # FU "Forward Progress" (read out horizontally) + m.d.sync += self.fwdl_o.eq(l.q & self.reg_i) + + # Register File Select (read out vertically) + m.d.comb += self.rselo.eq(l.q & self.go_i) + + return m + + def __iter__(self): + yield self.regt_i + yield self.issue_i + yield self.go_i + yield self.rsel_o + yield self.fwd_o + + def ports(self): + return list(self) + + class DependenceCell(Elaboratable): """ implements 11.4.7 mitch alsup dependence cell, p27 """ @@ -29,9 +72,9 @@ class DependenceCell(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules.dest_l = dest_l = SRLatch() # clock-sync'd - m.submodules.src1_l = src1_l = SRLatch() # clock-sync'd - m.submodules.src2_l = src2_l = SRLatch() # clock-sync'd + m.submodules.dest_l = dest_l = SRLatch(sync=False) # clock-sync'd + m.submodules.src1_l = src1_l = SRLatch(sync=False) # clock-sync'd + m.submodules.src2_l = src2_l = SRLatch(sync=False) # clock-sync'd # destination latch: reset on go_wr HI, set on dest and issue m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i) @@ -51,9 +94,9 @@ class DependenceCell(Elaboratable): m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.go_rd_i) # Register File Select (read out vertically) - m.d.comb += self.dest_rsel_o.eq(dest_l.q & self.dest_i) - m.d.comb += self.src1_rsel_o.eq(src1_l.q & self.src1_i) - m.d.comb += self.src2_rsel_o.eq(src2_l.q & self.src2_i) + m.d.sync += self.dest_rsel_o.eq(dest_l.q & self.dest_i) + m.d.sync += self.src1_rsel_o.eq(src1_l.q & self.src1_i) + m.d.sync += self.src2_rsel_o.eq(src2_l.q & self.src2_i) return m @@ -85,10 +128,10 @@ class DependencyRow(Elaboratable): self.dest_i = Signal(n_reg_col, reset_less=True) self.src1_i = Signal(n_reg_col, reset_less=True) self.src2_i = Signal(n_reg_col, reset_less=True) - self.issue_i = Signal(n_reg_col, reset_less=True) - self.go_wr_i = Signal(n_reg_col, reset_less=True) - self.go_rd_i = Signal(n_reg_col, reset_less=True) + self.issue_i = Signal(reset_less=True) + self.go_wr_i = Signal(reset_less=True) + self.go_rd_i = Signal(reset_less=True) self.dest_rsel_o = Signal(n_reg_col, reset_less=True) self.src1_rsel_o = Signal(n_reg_col, reset_less=True) @@ -125,19 +168,11 @@ class DependencyRow(Elaboratable): # --- # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr # --- - go_rd_i = [] - go_wr_i = [] - issue_i = [] for rn in range(self.n_reg_col): dc = rcell[rn] - # accumulate cell outputs for issue/go_rd/go_wr - go_rd_i.append(dc.go_rd_i) - go_wr_i.append(dc.go_wr_i) - issue_i.append(dc.issue_i) - # wire up inputs from module to row cell inputs (Cat is gooood) - m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i), - Cat(*go_wr_i).eq(self.go_wr_i), - Cat(*issue_i).eq(self.issue_i), + m.d.comb += [dc.go_rd_i.eq(self.go_rd_i), + dc.go_wr_i.eq(self.go_wr_i), + dc.issue_i.eq(self.issue_i), ] # --- @@ -161,11 +196,11 @@ class DependencyRow(Elaboratable): # --- # connect Reg Selection vector # --- + dest_rsel_o = [] + src1_rsel_o = [] + src2_rsel_o = [] for rn in range(self.n_reg_col): dc = rcell[rn] - dest_rsel_o = [] - src1_rsel_o = [] - src2_rsel_o = [] # accumulate cell reg-select outputs dest/src1/src2 dest_rsel_o.append(dc.dest_rsel_o) src1_rsel_o.append(dc.src1_rsel_o) @@ -177,6 +212,23 @@ class DependencyRow(Elaboratable): return m + def __iter__(self): + yield self.dest_i + yield self.src1_i + yield self.src2_i + yield self.issue_i + yield self.go_wr_i + yield self.go_rd_i + yield self.dest_rsel_o + yield self.src1_rsel_o + yield self.src2_rsel_o + yield self.dest_fwd_o + yield self.src1_fwd_o + yield self.src2_fwd_o + + def ports(self): + return list(self) + def dcell_sim(dut): yield dut.dest_i.eq(1) @@ -201,6 +253,11 @@ def dcell_sim(dut): yield def test_dcell(): + dut = DependencyRow(4) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_drow.il", "w") as f: + f.write(vl) + dut = DependenceCell() vl = rtlil.convert(dut, ports=dut.ports()) with open("test_dcell.il", "w") as f: