X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fscoreboard%2Fldst_matrix.py;h=b872155d8f05945a49c5aa43238a3507ab129944;hb=050709ca56f6cffba38303a8d24567816431832b;hp=daeb14274ecd478e6ba601885f2445535eae0e70;hpb=ea2950f85860622de92e32545ea96d968f1767f4;p=ieee754fpu.git

diff --git a/src/scoreboard/ldst_matrix.py b/src/scoreboard/ldst_matrix.py
index daeb1427..b872155d 100644
--- a/src/scoreboard/ldst_matrix.py
+++ b/src/scoreboard/ldst_matrix.py
@@ -1,15 +1,27 @@
+""" Mitch Alsup 6600-style LD/ST Memory Scoreboard Matrix (sparse vector)
+
+6600 LD/ST Dependency Table Matrix inputs / outputs
+---------------------------------------------------
+
+Relevant comments (p45-46):
+
+* If there are no WAR dependencies on a Load instruction with a computed
+  address it can assert Bank_Addressable and Translate_Addressable.
+
+* If there are no RAW dependencies on a Store instruction with both a
+  write permission and store data present it can assert Bank_Addressable
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=81
+
+"""
+
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
 
 from ldst_dep_cell import LDSTDepCell
 
-"""
-
- 6600 LD/ST Dependency Table Matrix inputs / outputs
- ---------------------------------------------------
-
-"""
 
 class LDSTDepMatrix(Elaboratable):
     """ implements 11.4.12 mitch alsup LD/ST Dependency Matrix, p46
@@ -29,8 +41,8 @@ class LDSTDepMatrix(Elaboratable):
         self.stwd_hit_i = Signal(n_ldst, reset_less=True) # store w/data hit in
 
         # outputs
-        self.ld_hold_st_o = Signal(n_ldst, reset_less=True) # load holds st out
-        self.st_hold_ld_o = Signal(n_ldst, reset_less=True) # st holds load out
+        self.ld_hold_st_o = Signal(reset_less=True) # load holds st out
+        self.st_hold_ld_o = Signal(reset_less=True) # st holds load out
 
     def elaborate(self, platform):
         m = Module()
@@ -45,8 +57,6 @@ class LDSTDepMatrix(Elaboratable):
         # ---
         # connect Function Unit vector
         # ---
-        lhs = Const(0) # start at const 0
-        shl = Const(0) # (does no harm)
         lhs_l = []
         shl_l = []
         load_l = []
@@ -56,17 +66,9 @@ class LDSTDepMatrix(Elaboratable):
         sh_l = []
         for fu in range(self.n_ldst):
             dc = dm[fu]
-            # OR the load-hold-store / store-hold-load cell outputs in...
-            _lhs = lhs
-            _shl = shl
-            lhs = Signal(reset_less=True)
-            shl = Signal(reset_less=True)
-            m.d.comb += [lhs.eq(_lhs | dc.ld_hold_st_o),
-                         shl.eq(_shl | dc.st_hold_ld_o)
-                        ]
             # accumulate load-hold-store / store-hold-load bits
-            lhs_l.append(lhs)
-            shl_l.append(shl)
+            lhs_l.append(dc.ld_hold_st_o)
+            shl_l.append(dc.st_hold_ld_o)
             # accumulate inputs (for Cat'ing later) - TODO: must be a better way
             load_l.append(dc.load_i)
             stor_l.append(dc.stor_i)
@@ -82,13 +84,13 @@ class LDSTDepMatrix(Elaboratable):
                      Cat(*sh_l).eq(self.stwd_hit_i),
                     ]
         # set the load-hold-store / store-hold-load OR-accumulated outputs
-        m.d.comb += self.ld_hold_st_o.eq(Cat(*lhs_l))
-        m.d.comb += self.st_hold_ld_o.eq(Cat(*shl_l))
+        m.d.comb += self.ld_hold_st_o.eq(Cat(*lhs_l).bool())
+        m.d.comb += self.st_hold_ld_o.eq(Cat(*shl_l).bool())
 
         return m
 
     def __iter__(self):
-        yield self.load_i  
+        yield self.load_i
         yield self.stor_i
         yield self.issue_i
         yield self.load_hit_i