X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fspr%2Fmain_stage.py;h=b3a49cb642e9509732eaa3763599180b718a41f9;hb=972f7cdd33ed6da0b57b2c39cddea6b0640c0ebc;hp=3e236a28bf321d050e0e140fd09551c14cfff68a;hpb=e19eeb30cb8ede0674f581e028c06d0cb22796a8;p=soc.git

diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index 3e236a28..b3a49cb6 100644
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -56,7 +56,8 @@ class SPRMainStage(PipeModBase):
             #### MTSPR ####
             with m.Case(MicrOp.OP_MTSPR):
                 with m.Switch(spr):
-                    # State SPRs first
+                    # State SPRs first, note that this triggers a regfile write
+                    # which is monitored right the way down in TestIssuerBase.
                     with m.Case(SPR.DEC, SPR.TB):
                         comb += state1_o.data.eq(a_i)
                         comb += state1_o.ok.eq(1)