X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fregfile%2Fsram_wrapper.py;h=297a935f6707036344c0504607a8791089cc964a;hb=07441462940dcf8412fef9ed2119a905bd084659;hp=5a455b811e6371f9db1bf69bce54eb18bab3e1c2;hpb=c35d59d0e8ae088f445fc64ade00885d9731ba71;p=soc.git

diff --git a/src/soc/regfile/sram_wrapper.py b/src/soc/regfile/sram_wrapper.py
index 5a455b81..297a935f 100644
--- a/src/soc/regfile/sram_wrapper.py
+++ b/src/soc/regfile/sram_wrapper.py
@@ -340,6 +340,16 @@ class PhasedDualPortRegfile(Elaboratable):
 
         return m
 
+    def ports(self):
+        return [
+            self.wr_addr_i,
+            self.wr_data_i,
+            self.wr_we_i,
+            self.rd_addr_i,
+            self.rd_data_o,
+            self.phase
+        ]
+
 
 class PhasedDualPortRegfileTestCase(FHDLTestCase):
 
@@ -660,6 +670,15 @@ class DualPortRegfile(Elaboratable):
                                    == self.dbg_wrote_phase)
         return m
 
+    def ports(self):
+        return [
+            self.wr_addr_i,
+            self.wr_data_i,
+            self.wr_we_i,
+            self.rd_addr_i,
+            self.rd_data_o
+        ]
+
 
 class DualPortRegfileTestCase(FHDLTestCase):