add MSR to verilator output debug reporting
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 7 Jan 2022 00:41:46 +0000 (00:41 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 7 Jan 2022 00:41:46 +0000 (00:41 +0000)
commit0500e35f4e596f9fc823916756648b0246a92cfd
treebef7379d91faff9d47f512cbf9e9edfdfca1db45
parent0c9588bd748910250b09f081ec45c244be187a74
add MSR to verilator output debug reporting
core.vhdl
fpga/top-generic.vhdl
soc.vhdl
verilator/microwatt-verilator.cpp