Wire up missing CRG / DDR3 clock control / reset signals
authorRaptor Engineering Development Team <support@raptorengineering.com>
Sat, 9 Apr 2022 20:06:12 +0000 (15:06 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Sun, 10 Apr 2022 17:40:34 +0000 (12:40 -0500)
commit0b5b93c30da61e27e91e04ae9213d0a504b8e17e
treebb582951988823e2c9d5319a350f7e72b8a3a1d5
parentcb6c333200bd5d1dbeeb2971a8f378ee5123deea
Wire up missing CRG / DDR3 clock control / reset signals
src/ecp5_crg.py
src/ls2.py