bug #672: invert testing in sv.minmax and add Rc=1
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 Dec 2023 15:38:26 +0000 (15:38 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:22 +0000 (19:26 +0000)
commit18c5bcfeec8e92d9744a4b76df642eff3451088c
tree56b592607599bbc3e80a270cefd2a15579af9a36
parent4c7fb5de738a1747534ede3e1e00b1c4fde87574
bug #672: invert testing in sv.minmax and add Rc=1
src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py