fix missing uart_top (ordering of read_verilog is now important)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 27 Feb 2022 13:45:22 +0000 (13:45 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 27 Feb 2022 13:45:22 +0000 (13:45 +0000)
commit1af7aae227754c895f026a45726f4cb15dc308cb
tree08b4c95efc29f83eaa1b76cadc1555ff29834c48
parent8d2423d2003180faf7beeb7d9216ea58f21e822b
fix missing uart_top (ordering of read_verilog is now important)
Makefile