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(parent: b6904a8) | patch
verilog: fix handling of nested ifdef directives
authorZachary Snow <zach@zachjs.com>
Thu, 25 Feb 2021 20:53:55 +0000 (15:53 -0500)
committerZachary Snow <zachary.j.snow@gmail.com>
Mon, 1 Mar 2021 17:28:33 +0000 (12:28 -0500)
commit1ec5994100510d6fb9e18ff7234ede496f831a51
tree77c8403f0ece00ad1b42e2e91f86befe0f736cactree
parentb6904a8e5344fcd01c1a0feea281cd7d7bf0f210commit | diff
verilog: fix handling of nested ifdef directives

- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
frontends/verilog/preproc.cc diff | blob | history
tests/simple/ifdef_1.v [new file with mode: 0644] blob
tests/simple/ifdef_2.v [new file with mode: 0644] blob
tests/verilog/include_self.v [new file with mode: 0644] blob
tests/verilog/include_self.ys [new file with mode: 0644] blob
tests/verilog/unmatched_else.ys [new file with mode: 0644] blob
tests/verilog/unmatched_elsif.ys [new file with mode: 0644] blob
tests/verilog/unmatched_endif.ys [new file with mode: 0644] blob