Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values
authorCatherine <whitequark@whitequark.org>
Sat, 11 Dec 2021 16:24:47 +0000 (16:24 +0000)
committerGitHub <noreply@github.com>
Sat, 11 Dec 2021 16:24:47 +0000 (16:24 +0000)
commit21fbdb6638bc00758dfe7aaac93c5805160168d5
tree6782061feabf37590b146aa194f66717160e146a
parent8e91857fabe75e032810bb09a22af1b18cb8172f
parent86f2804dc3f80cd74349c62888376c8596fb1856
Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values

write_verilog: dump zero width sigspecs correctly