gotten over the logic-dyslexia of what in/out mean in VHDL.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 1 Jan 2022 02:46:54 +0000 (02:46 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 1 Jan 2022 02:46:54 +0000 (02:46 +0000)
commit2260ca654d8552d6cb766b78df9888326b552714
tree6140b0273b7397b3d7e3d73342f6f341c15e7f91
parentd39213257ee364090cd07eb0e2fee2ed7940ce91
gotten over the logic-dyslexia of what in/out mean in VHDL.
BRAM can now be read/written using the contents of a file to initialise
from, at the command-line
Makefile
fpga/top-generic.vhdl
soc.vhdl
verilator/microwatt-verilator.cpp
wishbone_bram_wrapper.vhdl