hdl.ast: support division and modulo with negative divisor.
authorwhitequark <whitequark@whitequark.org>
Sat, 11 Dec 2021 08:52:14 +0000 (08:52 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 20:10:02 +0000 (20:10 +0000)
commit2e6ae1c7c047a050982e24af964ee98d6fb82f91
tree4ead9715355890d7cc01a342dcf5ae07b2a7f578
parent5c5e9bc0c6dd1dba61b3101654c3e6f18b331b64
hdl.ast: support division and modulo with negative divisor.

Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
docs/lang.rst
nmigen/back/cxxrtl.py
nmigen/back/rtlil.py
nmigen/back/verilog.py
nmigen/hdl/ast.py
tests/test_hdl_ast.py
tests/test_sim.py